A Hypertransport based low-latency reconfigurable testbed for message-passing developments

High-bandwidth, low-latency MPI implementations are of key importance for clustered, parallel computing machines. The performance of message-passing is based on the underlying network hardware, the network-interface architecture as well as the software design of the message-passing library and ultimately the parallel applications itself. This paper analyzes the application of the HTX-Board, a Hypertransport Extension (HTX) expansion board, in conjunction with the HT-Core, an open-source Hypertransport Intellectual Property Core for the development, rapid-prototyping and implementation of parallel message-passing systems. In particular the architecture and special hardware mechanisms will be presented and the performance thereof will be evaluated. This new platform enables highperformance, low-latency networking with end-to-end latencies of less than 1 μs using reconfigurable logic.